Subhrajit Das

Team Contributor at IIT Gandhinagar & University of Edinburgh (Oct 2025 - Present)

• Designing a dynamically scalable compute cluster using hundreds of Raspberry Pi 5s (wimpy nodes) to distribute large-scale matrix multiplication workloads.
• Leveraging the DPDK stack for high-throughput, low-latency inter-node communication, enabling efficient workload distribution across the dynamic cluster.
• Optimizing on-node performance (scale-up) using ARM AdvSIMD (NEON) extensions, with the goal of benchmarking the aggregate scale-out compute power against high-end GPUs.

Team Contributor at IIT Gandhinagar (Oct 2025 - Present)

• Ongoing project, selected in the Phase 1 of VSLID Design Contest 2026, investigating the implementation of lattice-based cryptographic algorithms on quantum hardware.
• Focuses on leveraging Qiskit Metal for designing and simulating quantum circuits. My role involves developing and optimizing quantum algorithms involving NTT for the targeted cryptographic schemes on the custom designed quantum hardware.

M.Tech. Thesis Work

• Advisor: Prof. Abhishek Bichhawat, Co-advisor: Prof. Yuvraj Patel (The University of Edinburgh)
• Designed high-performance faster data-parallel algorithms for large integer addition and subtraction using AVX512 for most cases.
• Achieved average execution-time speedup of 2.06x for addition and 2.32x for subtraction (up to 131k bits) compared to the GNU Multiple-Precision Arithmetic Library (GMP).
• Designed a faster Vedic-based multiplication algorithm for large integers using AVX512-IFMA for 256-bit operands, with execution-time speedup of 1.83x compared to the GMP library.
• Additionally, designed approximate variants of the proposed algorithms for large integer addition and multiplication, achieving average execution-time speedup of 2.52x and 2.80x, respectively, compared to GMP.

M.Sc. Thesis Work

• Advisor: Prof. Priya Ranjan Sinha Mahapatra, Co-advisor: Dr. Soumen Atta
• Designed and implemented an algorithm for solving maximal covering location problems using genetic and artificial bee colony algorithms.
• Achieved optimal benchmark results with CPLEX in 50% of cases, reducing the average computational time to 85.83 seconds, compared to over 1000 seconds for previous models, with an average gap of just 0.01%.

B.Sc. Project Work

• Designed a multiplier accumulate unit using reversible gates for low power consumption and heat dissipation.

Team Contributor

• Engineered an instant payment system using Parallel and Distributed Systems concepts.
• Facilitated seamless and secure interoperability between parties, similar to UPI.
• Implemented efficient transaction processing with load balancing, fault tolerance, and concurrency control to ensure high availability and scalability.

Individual Contributor

• Developed a simulation of a tennis game matching server where multiple players send requests for games: singles, doubles, male, female, or mixed.
• Utilized OpenMP threads to handle client requests and MPI calls for player communication.
• Managed the availability of limited tennis courts (4 courts) to continuously match players’ requests.
• Completed as part of the Parallel and Distributed Course at IIT Gandhinagar.