Subhrajit Das

Subhrajit Das is a Director’s PhD Fellow in the Department of Computer Science and Engineering at the Indian Institute of Technology Gandhinagar, advised by Prof. Abhishek Bichhawat. His research domain is within computer systems, with current work focusing on optimizing the performance of large integer arithmetic using parallelization. He holds a Master of Technology in Computer Science and Engineering from the same institute. Before that, he earned a Master of Science in Computer Science from the University of Kalyani and a Bachelor of Science (Honours) in Computer Science from the West Bengal State University.

Ph.D. in Computer Science and Engineering

2025 - Present · Indian Institute of Technology Gandhinagar, India

Master of Technology in Computer Science and Engineering

2023 - 2025 · Indian Institute of Technology Gandhinagar, India

Master of Science in Computer Science

2021 - 2023 · University of Kalyani, India

Bachelor of Science (Honours) in Computer Science

2018 - 2021 · Panihati Mahavidyalaya (West Bengal State University), India

DigitsOnTurbo: Accelerating Large Integer Arithmetic with Parallel Addition, Subtraction, and Vedic-Based Multiplication Using AVX512

M.Tech. Thesis Work

• Advisor: Prof. Abhishek Bichhawat, Co-advisor: Prof. Yuvraj Patel (The University of Edinburgh)
• Designed high-performance faster data-parallel algorithms for large integer addition and subtraction using AVX512 for most cases.
• Achieved average execution-time speedup of 2.06x for addition and 2.32x for subtraction (up to 131k bits) compared to the GNU Multiple-Precision Arithmetic Library (GMP).
• Designed a faster Vedic-based multiplication algorithm for large integers using AVX512-IFMA for 256-bit operands, with execution-time speedup of 1.83x compared to the GMP library.
• Additionally, designed approximate variants of the proposed algorithms for large integer addition and multiplication, achieving average execution-time speedup of 2.52x and 2.80x, respectively, compared to GMP.

Studies on Various Maximal Covering Location Problems using Genetic and Artificial Bee Colony Algorithms

M.Sc. Thesis Work

• Advisor: Prof. Priya Ranjan Sinha Mahapatra, Co-advisor: Dr. Soumen Atta
• Designed and implemented an algorithm for solving maximal covering location problems using genetic and artificial bee colony algorithms.
• Achieved optimal benchmark results with CPLEX in 50% of cases, reducing the average computational time to 85.83 seconds, compared to over 1000 seconds for previous models, with an average gap of just 0.01%.

Reversible Multiplier Accumulate Unit (B.Sc. Project)

B.Sc. Project Work

• Designed a multiplier accumulate unit using reversible gates for low power consumption and heat dissipation.

Instant Payment Gateway (IPG)

Team Contributor

• Engineered an instant payment system using Parallel and Distributed Systems concepts.
• Facilitated seamless and secure interoperability between parties, similar to UPI.
• Implemented efficient transaction processing with load balancing, fault tolerance, and concurrency control to ensure high availability and scalability.

TennisServe: A Parallel Game Matching Server with OpenMP & MPI

Individual Contributor

• Developed a simulation of a tennis game matching server where multiple players send requests for games: singles, doubles, male, female, or mixed.
• Utilized OpenMP threads to handle client requests and MPI calls for player communication.
• Managed the availability of limited tennis courts (4 courts) to continuously match players’ requests.
• Completed as part of the Parallel and Distributed Course at IIT Gandhinagar.

Teaching Assistant

Jul 2023 - Present · Indian Institute of Technology Gandhinagar, India

Guest Lecture on RAID

Apr 2025 · Indian Institute of Technology Gandhinagar, India

Principal Instructor

Nov 2024 · Indian Institute of Technology Gandhinagar, India

• Performance and Usability in Systems Security